இன்டர்நேஷனல் ஜர்னல் ஆஃப் அட்வான்ஸ்மென்ட்ஸ் இன் டெக்னாலஜி
திறந்த அணுகல்

சுருக்கம்

Dynamic Power Reduction of Digital Circuits by Clock Gating

Padmini G.Kaushik, Sanjay M.Gulhane,Athar Ravish Khan

Clock gating technology can reduce the consumption of clock signals’ switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all adders. However, the enable functions of clock gate can be further simplified, and the average number of adders driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved.